Inter-Kernel Data Reuse and Pipelining on Chip-Multiprocessors for Multimedia Applications

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
The increasing demand for low power and high performance multimedia embedded systems has motivated the need for effective solutions to satisfy application bandwidth and latency requirements under a tight power budget. As technology scales, it is imperative that applications are optimized to take full advantage of the underlying resources and meet both power and performance requirements. The authors propose a methodology capable of discovering and enabling parallelism opportunities via code transformations, efficiently distributing the computational load across resources, and minimizing unnecessary data transfers.

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