Inter-Process Communication with Network-on-Chip Using CDMA Technique
In this paper, a novel implementation of CDMA NoC is proposed. Performance analysis is done for the physical design parameters of CDMA NoC. The present work retains the advantages of serial transmission without the need for a specialized serializer and de-serializer. The asynchronous circuit design with combinational logic (Gate level design) is used for transmission and receiving circuits, along with IP-cores and reduces the processing time and resource utilization. The embedded BlockRAM (BRAM) provides the area optimization when implemented in FPGA devices. The use of asynchronous pipelined core design process increases the operating frequency as well. In this paper, acknowledgement is used as an enabling signal and thereby reduces the leakage current in the repeaters during idle state.