Interconnect Design Considerations for Large NUCA Caches

Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposals advocate splitting the cache into a large number of banks and employing a Network-on-Chip (NoC) to allow fast access to nearby banks (referred to as Non-Uniform Cache Architectures (NUCA). Most studies on NUCA organizations have assumed a generic NoC and focused on logical policies for cache block placement, movement, and search.

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