Journal of Semiconductor Technology and Science (JSTS)
Moore's law has driven silicon technology scale down aggressively and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of the authors' knowledge. In this paper, they introduce industrial applications of low power design methodologies for the decrease of leakage current.