Investigating the Impact of NBTI on Different Power Saving Cache Strategies

Provided by: edaa
Topic: Storage
Format: PDF
The occupancy of caches has tended to be dominated by the logic bit value '0' approximately 75% of the time. Periodic bit flipping can reduce this to 50%. Combining cache power saving strategies with bit flipping can lower the effective logic bit value '0' occupancy ratios even further. The authors investigate how Negative Bias Temperature Instability (NBTI) affects different power saving cache strategies employing symmetric and asymmetric 6- Transistor (6T) and 8T Static Random Access Memory (SRAM) cells.

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