Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks

Provided by: edaa
Topic: Hardware
Format: PDF
High reliability against noise, low energy consumption and high performance are key objectives in the design of on-chip networks. Recently some researchers have considered the various trade-offs between two of these objectives. However, as the authors will argue later, the three design objectives should be considered jointly and simultaneously. In this paper, the authors analyze the impact of various error-control schemes on the simultaneous trade-off between reliability, performance and energy when voltage swing varies. They provide a detailed comparative analysis of the error-control schemes using analytical models and SPICE simulations.

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