Joint Dynamic Supply Voltage and Clock Frequency Scaling in Fine-Grain GALS Multiprocessors
In this paper, the authors examine techniques for reducing both dynamic and leakage power of a multiple voltage domain architecture while minimizing area and performance overhead. Variations in the workload across domains allow for reducing voltage and frequency to save power. A dynamic voltage and frequency scaling circuit is designed as a wrapper to the core logic. The design is implemented on AsAP architecture with an 11.5% area overhead. On a 9 processor JPEG application, a 68% power saving was achieved, with a minimum of a 7% performance overhead.