Joint Exploitation of Horizontal/Vertical Parallelism and Operation Chaining for Flexible DSP Synthesis

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Provided by: National Technical University of Athens
Topic: Hardware
Format: PDF
In this paper, the authors present a new methodology for the synthesis of high performance flexible datapath, targeting the computationally intensive DSP kernels of modern embedded applications. The proposed methodology is based on a novel coarse-grained reconfigurable architectural template, which enables the combined exploitation of the horizontal/vertical parallelism along with the operation chaining opportunities found in the application's behavioral description. The proposed approach delivers average latency, area and energy reductions of about 17%, 19% and 24% respectively, compared to other coarse grained reconfigurable datapath.
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