Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms

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Topic: Hardware
Format: PDF
Application models are often disregarded during the design of Multi-Processor Systems-on-Chip (MPSoC). This is due to the difficulties of capturing the application constraints and applying them to the design space exploration of the platform. In this paper, the authors propose an application modeling formalism that supports joint validation of application and platform models. To support designers on the trade-off analysis between accuracy, observability, and validation speed, they show that this approach can handle the successive refinement of platform models at multiple abstraction levels.
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