Provided by: Institute of Electrical & Electronic Engineers
Date Added: May 2014
The energy in FPGA computations can be dominated by data communication energy, either in the form of memory references or data movement on interconnect (e.g., over 75% of energy for single processor gaussian mixture modeling, window filtering, and FFT). In this paper, the authors explore how to use data placement and parallelism to reduce communication energy. They further introduce a new architecture for embedded memories, the Continuous Hierarchy Memory (CHM), and show that it increases the opportunities to reduce energy by strategic data placement.