Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation

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Provided by: European Design and Automation Association
Topic: Hardware
Format: PDF
Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shipped to the customers fault-free. However, at-speed tests have been known to create higher-than-average switching activity, which normally is not accounted for in the design of the power supply network. This potentially creates conditions for additional delay in the chip; causing it to fail during test. In this paper, the authors propose a pattern compaction technique that considers the layout and gate distribution when generating transition delay fault patterns.
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