Layout-Conscious Random Topologies for HPC Off-Chip Interconnects

In this paper the authors propose two new methods for generating random topologies and their physical layout on a floor-plan: randomize links after optimizing the physical layout, or optimize the layout after randomizing links. The first method randomly swaps link endpoints for a given non-random topology for which a good physical layout is known. The resulting topology has the same cable length and cable packaging as the original topology, but achieves lower communication latency. The second method creates a random topology with random links picked so that they will not lead to a long physical cable length, and then solves a constrained optimization problem to compute a physical layout that minimizes aggregate cable length.

Provided by: University of Hawaii Topic: Data Centers Date Added: Jan 2013 Format: PDF

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