Layout Designing for Different Full Adder Topologies at 0.18um Technology Node

In this paper, VLSI layout designing and optimization techniques for different full adder topologies like Complementary Metal - Oxide - Semiconductor full adder (CMOS), Transmission Gate full Adder (TGA), Complementary Pass transistor Logic full adder (CPL) and domino full adder has been discussed. Power consumption and propagation delay are the major issue for low voltage level circuit application designing in recent years. Full adders are the very important circuit element for calculating the basic four mathematical operations (addition, subtraction, multiplication and division) functions in Integrated circuits.

Provided by: Iosrjournals Topic: Hardware Date Added: Oct 2014 Format: PDF

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