Layout Driven Data Communication Optimization for High Level Synthesis

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Provided by: edaa
Topic: Hardware
Format: PDF
High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the final circuit layout. In this paper, the authors present a physically aware design flow for mapping high level application specifications to a synthesizable register transfer level hardware description. They study the problem of optimizing the data communication of the variables in the application specification. Their algorithm uses floorplan information that guides the optimization.
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