Institute of Electrical & Electronic Engineers
As more and more transistors can be integrated into a single chip, the rich transistor resource enables Chip Multi-Processor (CMP) architecture, which in turn produces heavy memory loads and therefore generates tremendous stress on the main memory. On the other hand, the memory requests from multiple cores render high random behavior so that low row buffer locality can be exploited. The poor spatial locality makes it more challenging to design a memory controller with satisfied performance. Given the low row buffer locality, the close-page policy that closes the entire row buffer immediately after the data access is preferable in the CMP.