Provided by: Academy & Industry Research Collaboration Center
Date Added: Aug 2012
This paper presents a high-throughput memory efficient decoder for Low Density Parity Check (LDPC) codes in the high-rate wireless personal area network application. The novel techniques which can apply to the authors' selected LDPC code is proposed, including parallel blocked layered decoding architecture and simplification of the WiGig networks. They use Real Time - Performance Evaluation Process Algebra (RTPEPA) to evaluate a typical LDPC Decoder system's performance. The approach is more convenient, flexible, and lower cost than the former simulation method which needs develop special hardware and software tools.