Leakage current reduction in CMOS circuits using stacking effect

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Provided by: International Journal of Application or Innovation in Engineering & Management (IJAIEM)
Topic: Hardware
Format: PDF
Due to the growing impact of sub-threshold and gate leakage, static leakage is contributing more and more towards the power dissipation in deep submicron Nano CMOS technology. There have been many works on sub-threshold leakage and techniques to reduce it, such as controlling the input vector to the circuit in standby mode, forcing stack and body bias control. In this tutorial paper the authors have reviewed the leakage current with change in drain source, gate and bulk voltages for 4 different submicron technologies using the latest PTM models.
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