Leakage Power Reduction in Wallace Tree Multiplier Using Current Comaprison Based Domino Logic Full Adders

A lower power current comparison based domino logic 44 Wallace tree multiplier is proposed. Here the multiplier is designed by using low leakage high speed full adders. These full adders uses current comparison based domino logic to achieve low leakage and high speed. The technique which is utilized in this paper is based on comparison of mirrored current of the pull-up network with its worst leakage case current. This technique decreases the parasitic capacitance on the dynamic node, yielding a smaller keeper for wide fan-in gates to implement fast and robust circuits.

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Journal of Theoretical and Applied Information Technology