LEMap: Controlling Leakage in Large Chip-Multiprocessor Caches Via Prole-Guided Virtual Address Translation

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Provided by: Indian Institute of Technology Kanpur
Topic: Hardware
Format: PDF
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last level cache. However, larger caches threaten to dramatically increase the leakage power as the industry moves into deeper sub-micron technology. In this paper, with the aim of reducing leakage energy the authors introduce LEMap (Low Energy Map), a novel virtual address translation scheme to control the set of physical pages mapped to each bank of a large multi-banked non-uniform access L2 cache shared across all the cores.
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