The University of Tulsa
The DRAM main memory system in modern servers is largely homogeneous. In recent years, DRAM manufacturers have produced chips with vastly differing latency and energy characteristics. This paper provides the opportunity to build a heterogeneous main memory sys-tem where different parts of the address space can yield different latencies and energy per access. This paper has explored smart placement of pages with high activities. In this paper, the authors propose a novel alternative to exploit DRAM heterogeneity.