Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip

Provided by: Institute of Electrical and Electronics Engineers Topic: Mobility Date Added: Feb 2010 Format: PDF
Latency-insensitive design is a methodology for System-on-Chip (SoC) design that simplifies the reuse of intellectual property cores and the implementation of the communication among them. This simplification is based on a system-level protocol that decouples the intra-core logic design from the design of the inter-core communication channels. Each core is encapsulated within a shell, a synthesized logic block that dynamically controls its operation to interface it with the rest of the SoC and absorb any latency variations on its I/O signals. In particular, a shell stalls a core whenever new valid data are not available on the input channels or a downlink core has requested a delay in the data production on the output channels.

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