Provided by: International Journal of Scientific Engineering and Technology
Date Added: Oct 2012
In this paper the authors provide new low power solutions for Very Large Scale Integration (VLSI) designers. Especially, the authors focus on leakage power reduction. Although leakage power was negligible at 0.18μ technology and in nano scale technology, such as 0.07μ, leakage power is almost equal to dynamic power consumption. This paper presents heretofore unexplored methods for low-power VLSI design. In particular, the Low Leakage approach provides what may be the best solution for VLSI designers concerned about the twin problems of low static power and maintenance of VLSI logic state during sleep mode.