University of Central England in Birmingham
In this paper, the authors propose a novel information redundancy scheme to protect microprocessors from transient faults. Similar to traditional information redundancy techniques such as ECC, their approach does not require redundant execution in order to detect faults. Instead, redundant bits are used to encode correct instruction execution. However, their mechanism is fundamentally different from traditional information redundancy approaches in how the redundant bits are generated. Rather than using generic information theory, their scheme exploits a program locality, named Limited Variance in Data Values (LVDV) to encode instruction execution. In their proposed scheme, a single table tracks the expected behavior of instructions and is used to protect multiple logic units in the pipeline at the same time.