Provided by: Association for Computing Machinery
Date Added: Nov 2013
As cache hierarchies become deeper and the number of cores on a chip increases, managing caches becomes more important for performance and energy. However, current hardware cache management policies do not always adapt optimally to the applications behavior: e.g., caches may be polluted by data structures whose locality cannot be captured by the caches, and producer-consumer communication in-curs multiple round trips of coherence messages per cache line transferred. The authors propose load and store instructions that carry hints regarding into which cache(s) the accessed data should be placed.