Low Impenetrable Packed Fused Floating Point FFT with Area Optimization

Provided by: International Journal of Engineering Trends and Technology
Topic: Hardware
Format: PDF
FFT processor with pipelining concept is a special processor for DFT derivation using fast innovative algorithms. This paper presents implementation of a pipelined complex fused FFT processor for multi-purpose applications. In this paper, both radix-2 and radix-4 floating point butterflies are implemented with more efficiency and with the two fused floating point operations. Reusability is the main concern in this paper. By using fusing concept, common required components are shared by different operations. Both discrete and fused radix processors are implemented; compared in regarded with area-wise.

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