University of Tasmania
On-chip communication has two different type of architecture which can be classified as Bus and mesh based Networks-on-Chip (NoC). Each of them has different features and applications. In this paper, the authors construct the hybrid architecture with using bus and mesh NOC architecture. In the hybrid architecture, heavy communication affinity IP cores are placed in the same subsystem. and this large mesh NoC get partitioned into several subsystems and one on one individual IPs, so that there is the reduction in the transmission latency of NoC. Efficient partition and mapping algorithm is proposed for reduction of the latency on the hybrid NOC architecture. It shows that an average latency improvement of 17.6% and more can be obtained when compared with the conventional mesh NoC architecture.