Provided by: Institute of Electrical & Electronic Engineers
Date Added: Sep 2010
In frame memory recompression, decompression latency consists of two components, i.e., memory access cycles for compressed data fetch, and decompression time. Compared to most earlier works which mainly focused on the compression ratio and, therefore, only reducing memory access cycles, this paper proposes a low-latency variable-length coding method called Non-zero Bit Selection scheme (NBS). The proposed NBS enables highly parallel decompression achieving a three-cycle decompression for an 8x8 block, compared to previous methods requiring as many as twelve clock cycles for the case of exponential Golomb code.