Low Pin-Count Debug Interfaces for Multi-Device Systems

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Provided by: Politecnico di Bari
Topic: Hardware
Format: PDF
IEEE Std 1149.1-2001 standard test access port and boundary-scan architecture is widely used as a debug interface, providing a path for a debugger to access debug components in complex System-on-Chips (SoCs). By its very nature JTAG accommodates systems containing multiple devices. However, JTAG was primarily intended as a component and board test interface, and is not ideally suited as a debug interface. Its shortcomings have led the industry to search for an alternative. As a result, JTAG interfaces have started to be displaced by dedicated debug interfaces.
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