Low Power 4-2 Compressor for Arithmetic Circuits
Most of the VLSI circuits used adders as a crucial portion, since they form the base element of all arithmetic functions. Increasing demand for portable equipment's requires area and power efficient VLSI circuits. This paper presents 4-2 compressor using two different 8T full adder designs. The aim of this paper is to reduce the power consumption of 4-2 compressor without compromising the speed and performance. All pre-layout and post-layout simulations have been performed at 45nm technology on Tanner EDA tool version 12.6 and compared in terms of power consumption, Power-Delay Product (PDP) over various input voltages, temperatures and frequencies.