Low Power 9T Full Adder Using Inversion Logic
The low-power clubbed with low-energy has become an important issue in recent trends of VLSI. This paper presents pre-layout and post-layout simulations of a new 9T full adder cell at low voltages. The main objective of design is low power consumption and full voltage swing which is achieved at low supply voltage. The proposed design shows its superiority against existing adder in terms of power consumption, Power-Delay Product (PDP), temperature sustainability and noise immunity. All the pre-layout and post-layout simulations have been performed at 45nm technology on Tanner EDA Tool version 12.6.