Low-Power Adaptive Pipelined MPSoCs for Multimedia: An H.264 Video Encoder Case Study

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Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
Pipelined MPSoCs provide a high throughput implementation platform for multimedia applications, with reduced design time and improved flexibility. Typically a pipelined MPSoC is balanced at design-time using worst-case parameters. Where there is a widely varying workload, such designs consume exorbitant amount of power. In this paper, the authors propose a novel adaptive pipelined MPSoC architecture that adapts itself to varying workloads. Their architecture consists of main processors and auxiliary processors with a distributed run-time balancing approach, where each main processor, independent of other main processors, decides for itself the number of required auxiliary processors at run-time depending on its varying workload.
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