International Journal of Scientific and Research Publication (IJSRP)
Viterbi Decoder (VD) employed in digital wireless communication plays a dominant role in the overall power consumption of Trellis Coded Modulation (TCM) decoder. Power reduction in VD could be achieved by reducing the number of states. A pre-computation architecture with T-algorithm was implemented for this purpose, and when the authors compare this result with full trellis VD, this approach significantly reduces power consumption without degrading decoding speed much. Low power design of VD for TCM systems with reliable delay is presented in this paper.