Low Power Adder Based ANN

Provided by: International Journal of Computer Applications
Topic: Hardware
Format: PDF
In this paper, the authors present an overview of data path realizations of the hardware neural network models which perform massive parallel operations for best results and real time applications. Digital implemented neural models processing element, adder with low power consumption is proposed for real-time multimedia applications. Proposed adder is illustrated in the 2-3-1 tree layer Artificial Neural Network (ANN). Designs were modeled with Verilog HDL and implemented in FPGA domain by targeting the Virtex-7 device.

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