Low-Power Analysis of Various 1-Bit SRAM Cells Using Spice

Provided by: Creative Commons Topic: Hardware Format: PDF
The need for low-power memory design is becoming a major issue in high-performance digital systems such as microprocessors, Digital Signal Processors (DSPs) and other applications. This paper discusses 7T, 6T, 5T & 4T SRAM cells configurations for the same. Six Transistor (6T) SRAM Cells are the main choice for today's cache applications. The Static Noise Margin (SNM) of 6T SRAM cell is highest in all memory cells, so the stability is highest in this cell. The circuit is characterized by using the 32nm technology. Delay of the 7T cell is 0.5ns and leakage power dissipation in standby mode is 1.25×10-9 watts.

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