Low Power and Area Efficient Folded Architecture for Row Bypassing Multiplier Using FPGA

Provided by: IRD India
Topic: Hardware
Format: PDF
Optimizing power consumption and reducing hardware complexity are the most important criteria for the fabrication of DSP architectures. DSP operation must be completed within fixed time which demands the usage of high speed multiplier that consumes low power. In this work, a methodology to determine the best solution to this problem is presented by designing parallel and folded row bypassing multiplier. The performance of row bypassing multiplier is analyzed using a 8bit multiplication operation. The design uses four 4×4 row bypassing multiplier blocks based on ripple carry adder.

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