Low Power Architecture Design of De-Blocking Filter and Hardware Implementations in H.264/AVC

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Provided by: Creative Commons
Topic: Hardware
Format: PDF
An adaptive in-loop De-blocking Filter (DF) is standardized in H.264/AVC to reduce blocking artifacts and improve compression efficiency. This paper proposes low power DF architecture with hybrid and intelligent edge skip filtering order. The authors further adopt a four-stage pipeline to boost the speed of DF process and the proposed Horizontal Edge Skip Processing Architecture (HESPA) offers an edge skip aware mechanism for filtering the horizontal edges that not only reduces power consumption but also reduces the filtering processes down to 100 clock cycles per Macro-Block (MB).
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