Low-Power Architectures and Self-Calibration Techniques of DAC for SAR-ADC implementation

Provided by: International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE)
Topic: Hardware
Format: PDF
SAR-ADC is best suited for low power applications where power has a trade-off with speed. Use of redundant circuitry reduces the on chip area making it cost effective. DAC is one of the components of SAR-ADC that introduces error voltage due to mismatch and consumes large power other than comparator. Low power DAC architectures have been studied and analyzed. To account for capacitor mismatch issues self-calibration techniques have been discussed and analyzed for 14-bit DAC implementation.

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