Low Power Area-Efficient Adiabatic Vedic Multiplier

In this paper, the authors describe adiabatic Vedic multiplier using Efficient Charge Recovery Logic (ECRL). Today power dissipation minimization is the basic principle in making any electronic product portable. Even though there has been a decrease in circuit operating voltages, significant power is lost in switching elements (transistors). With adiabatic logic most of the energy is restored to the source instead of dissipating as heat. Proposed paper focuses on the design of low power and area-efficient adiabatic Vedic multiplier using TSMC0.18µm CMOS process technology in tanner tool v13.

Provided by: International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (IJAREEIE) Topic: Hardware Date Added: Aug 2014 Format: PDF

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