Low Power BIST Implementation of Test Pattern Generation Based on Accumulator

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Provided by: International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE)
Topic: Hardware
Format: PDF
The hardware overhead and fault coverage of a circuit is an important problem in integrated circuits and systems. To overcome this problem pseudorandom Built-In-Self-Test (BIST) generators have been widely utilized to test integrated circuits and systems. A PseudoRandom Pattern Generator (PRPG) is used for Generating Test Patterns (TPG). A weighted Pseudorandom Built-In-Self-Test (BIST) schemes have been utilized in order to drive down the number of vectors to achieve complete fault coverage in BIST applications. Weighted sets comprising three weights, namely 0, 1, and 0.5 have been successfully utilized so far for test pattern generation, since they result in both low testing time and low consumed power.
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