Low Power CMOS 1-Bit Full Adder Cell Based on Voltage Scaling

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Provided by: IOSR Journal of Engineering
Topic: Mobility
Format: PDF
Operating an Integrated circuit at the prescribed Voltage scaling (constant field scaling) is preferable for reliable circuit operation under temperature fluctuations. In this paper, the authors proposed to design 1 - bit full adder by "Changing the threshold voltage and W/L ratio" under temperature variation insensitive conditions. They measured power consumption, leakage current, noise margin, layout area, etc parameters. The results are compared with the previous work and shown that Power is saved 92%, 1% of leakage current and 15% of noise margin. They have performed simulations using 90 Nanometer (nm) Micro wind 3 CMOS layout CAD Tool for design.
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