Carry SeLect Adder (CSeLA) is mainly used to alleviate the propagation delay caused by carry bit and upon which sum bit is generated. It produces n+1 sum from n bits. In this paper, the author's present simple Gate level implementation of regular Carry Select Adder is compared with their proposed work. Based on the comparison made in terms of power, delay and area, it is found that there is considerable reduction in area and power with delay overhead. Both regular and proposed methods are modeled using 180nm CMOS technology. From the results obtained, it is clear that proposed CSeLA is better than regular CSeLA.