International Journal of Computer Technology and Electronics Engineering
CORDIC (COrdinate Rotation for DIgital Computers) an economical replacement for the use of Multipliers, is a fast and efficient algorithm that can be used for any type of digital signal processing architectures (Microprocessor). The latest trends in VLSI technology enhance different ways of implementing the CORDIC architecture. This paper focuses on an ASIC implementation of a CORDIC architecture with a merit of reduced latency and power. The power reduction is done by using a reliable scheme of controlling the switching activity of the clocks used in the design.