Low-Power Decimation Filter for 2.5 GHz Operation in Standard-Cell Implementation
A low-power decimation filter for very high-speed over-sampling analog to digital converters implemented in semi-custom design style is presented. The possibility to use a deep-sub-micron digital standard cell library in a VHDL based automated design flow to replace work intense full-custom design is demonstrated. The choice of a polyphase non-recursive decimation filter structure is explained and some aspects of synthesis and routing influencing the design are discussed. Results after layout and their analysis are presented for different filter structures, which demonstrate the correctness of the designed decimation filter at the specified clock speed of 2.56 GHz with a power consumption of 1.2 mW.