International Journal of Engineering Trends and Technology
Low power memory is required today most priority with also high stability. The power is most important factor for today's technology, so the power reduction for one cell is vital role in memory design techniques. In this paper, the authors introduced some design circuit techniques for low power design. Leakage current in standby mode is the major part of power loss. They concentrate on the technique that to reduce the leakage current in standby mode. The one CMOS transistor leakage current due to various parameter is the vital role of power consumption.