Low Power Design for D-Flip Flop
In this paper, the authors enumerate the low power, high speed D-flip flop based on comparison between the various techniques i.e. double edge triggering flip flop, low swing double edge flip flop, multi threshold CMOS and conditional data mapping flip flop. In this paper, various designs are presented by connecting limited number of transistors and as the transistors used have small area and low power consumption, they can be used in buffers, registers, microprocessors, etc. The comparison is based on number of factors like leakage current, short circuit current, data activity, etc.