Low Power Design for D-Flip Flops- MTCMOS Techniques
Power consumption is a major bottleneck of system performance. Power consumption plays an essential role in any integrated circuit and is noted as one of the top three challenges in International technology roadmap. In this paper, the authors enumerate the low power; high speed D-flip flop based on comparison between the various techniques i.e. double edge triggering flip flop, low swing double edge flip flop, multi threshold CMOS and conditional data mapping flip flop. In this paper, a broad idea of different proposed techniques for low power D flip flops are presented along with the facts that prove MTCMOS technique to be the most suitable one.