In technology improvement power dissipation has one of the major factors well known short circuit dissipations, leakage dissipations and dynamic switching dissipations are major power dissipation sources of CMOS chips. For reducing power dissipation in CMOS logic blocks various techniques were there among these techniques most effective new technique implemented with low power dissipation. That is "Low Power design of Asynchronous Fine-grain Power gated Logic" (LPAFPL). Low power AFPL is a new logic family. It consists of ECRL (Efficient Charge Recovery Logic gate), pipeline system, C-element and Partial Charge Reuse mechanism (PCR).