International Journal of Emerging Technology in Computer Science and Electronics ( IJETCSE)
Reducing power consumption in Very Large Scale Integrated Circuits (VLSI) design has become an interesting research area. Most of the portable devices available in the market are battery driven. These devices impose tight constraint on the power dissipation. Reducing power consumption in such devices can be improving using clock gating technique. The proposed designs eliminate the large capacitance present in the precharge node of several designs by following a split dynamic node structure to separately drive the output pull-up and pull-down transistors.