Low Power Dual Edge - Triggered Static D Flip-Flop
In this paper, the authors enumerate new architecture of low power Dual-Edge Triggered Flip-Flop (DETFF) designed at 180nm CMOS technology. In DETFF, same data throughput can be achieved with half of the clock frequency as compared to Single-Edge Triggered Flip-Flop (SETFF). In this paper, conventional and proposed DETFF are presented and compared at same simulation conditions. The post layout experimental results comparison shows that the average power dissipation is improved by 48.17%, 41.29% and 36.84% when compared with SCDFF, DEPFF and SEDNIFF respectively and improvement in PDP is 42.44%, 33.88% and 24.69% as compared to SCDFF, DEPFF and SEDNIFF respectively.