International Association of Engineers
A low power and high performance 1-bit full adder cell is proposed. The 8T full adder technique has been used for the generation of XOR function. Twelve state-of-the-art 1-bit full adders and one proposed full adder are simulated with HSPICE using 0.18Î¼m CMOS technology at 1.8V supply voltage. By optimizing the transistor size in each stage the power and delay are minimized. The results of post-layout simulation compared to similar reported ones illustrate significant improvement. Simulation results show great improvement in terms of Power-Delay-Product (PDP). The power consumption of this adder is 200nw.